1. Field of the Invention
The present invention relates to the field of digital computer systems, and more particularly, to the determination of a memory location or accesses from the bus masters of one bus of a system which has two or more buses.
2. Description of Related Art
In computer systems, electronic chips and other components are connected with one another by buses. A variety of components can be connected to the bus providing intercommunication between all of the devices that are connected to the bus. One type of bus which has gained wide industry acceptance is the industry standard architecture (ISA) bus. The ISA bus has twenty-four (24) memory address lines which therefore provides support for up to sixteen megabytes of memory. The wide acceptance of the ISA bus has resulted in a very large percentage of manufactured devices being designed for use on the ISA bus. However, higher-speed input/output devices commonly used in computer systems require faster buses. A solution to the general problem of sending and receiving data from the processor to any high-speed input device is a local bus. Unlike the ISA bus, which operates relatively slowly with limited bandwidth, a local bus communicates at system speed and carries data in 32-bit blocks. Local bus schemes remove from the main system bus those interfaces that need quick response, such as memory, display, and disk drives. One such local bus that is gaining acceptance in the industry is the peripheral component interconnect (PCI) bus. The PCI bus can be a 32 or 64-bit pathway for high-speed data transfer. Essentially, the PCI bus is a parallel data path provided in addition to an ISA bus. The system processor and memory can be attached directly to the PCI bus, for example. Other devices such as graphic display adapters, disk controllers, etc. can also attach directly to the PCI bus.
A bridge chip is provided between the PCI bus and the ISA bus in order to provide communication between devices on the two buses. The bridge chip essentially converts ISA bus cycles to PCI bus cycles, and vice versa.
Many of the devices attached to the PCI bus and the ISA bus are master devices that conduct processing independently of the bus or other devices. Other components coupled to the bus are considered to be slaves or targets that accept commands and respond to requests of a master. The PCI bus has an addressing capability of 32 bits to provide for 4 gigabytes of memory access. A master on the ISA bus can access a memory location in the memory on the PCI bus.
In the prior art systems using a PCI bus and an ISA bus, the bridge chip between the PCI bus and ISA bus included programmable registers which contain information as to which bus a particular segment of memory is mapped to. When the direct memory access (DMA) controller of the bridge chip performs a transfer cycle, the bridge chip would compare the memory address received from the ISA DMA bus master to the values in the registers. This requires the use of a PCI decoder as well as an ISA decoder. When a range comparison in a particular decoder indicates that the segment of memory is mapped to a particular bus, the memory cycle is performed on that particular bus only and not on the other bus. When an ISA bus master is performing a memory cycle on the ISA bus, the memory address is also compared by the PCI decoder in the bridge chip and the memory cycle is performed on the PCI bus if a range comparison occurs.
The prior art arrangement using a PCI decoder, an ISA decoder, and supporting software for setting up ranges requires a relatively large amount of hardware and software for implementation.